This invention relates to semiconductor devices, and more particularly, to scanning electron microscope analysis of semiconductor devices.
Manufacturing semiconductor devices efficiently depends on having accurate estimates of the thickness of the devices"" layers, which may be as small as a few tens of nanometers currently. Underestimating the thickness of a layer may lead to improper contact, and consequently an inoperative device, due to insufficient etching. Overestimating the thickness of a layer may lead to altered electrical properties, due to excessive etching. Additionally, inaccurate estimates may cause problems with thin film deposition and cleaning. Furthermore, not being able to accurately estimate the thickness of materials used to form the devices may lead to inaccurate characterization of the etch rate itself, not to mention selectivity.
To achieve accurate estimates of the size of such small structures, manufacturers typically rely upon an electron microscope to measure the layers of sample devices. Scanning electron microscopes, for example, can typically resolve layers that are a few tens of Angstroms in thickness.
Unfortunately, scanning electron microscopes have been observed to generate inaccurate measurements for new generation semiconductor devices. Furthermore, various coatings used to reduce charge build-up on semiconductor devices being analyzed by scanning electron microscopes, such as gold, palladium, platinum, aluminum, titanium, and cobalt, may mask the structural features of the devices, making observation and analysis difficult.
The present invention substantially reduces and/or eliminates at least some of the problems and disadvantages associated with previously developed assemblies and methods for scanning electron microscope analysis of semiconductor devices. Accordingly, the present invention, at least in particular embodiments, provides a system and method for reducing deformation of a semiconductor device being examined by a scanning electron microscope while still allowing relatively small structural features of the device to be observed.
In certain embodiments, an assembly for improved scanning electron microscope analysis of semiconductor devices includes a structure and a coating on at least part of the surface of the structure. The structure includes a first layer and a second layer, the second layer shrinking substantially when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV. The coating includes Iridium and is of sufficient thickness to reduce shrinkage of the second layer to approximately a predetermined amount when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV.
In particular embodiments, a method for improved scanning electron microscope analysis of semiconductor devices includes providing a structure including a first layer and a second layer, the second layer shrinking substantially when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV. The method also includes coating at least part of the surface of the structure with a material including Iridium, wherein the coating is of sufficient thickness to reduce shrinkage of the second layer to approximately a predetermined amount when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV.
The present invention possesses several technical features. For example, because the coating may prevent at least one layer of the structure from shrinking substantially when the structure is being examined by a scanning electron microscope, measurements of the layers of the structure may be made with increased accuracy. This allows increased semiconductor manufacturing efficiency, due to reduction of etching, thin film deposition, and cleaning problems because of inaccurate estimates and to better characterization of the etch rate itself and selectivity. Moreover, because materials that shrink substantially during scanning electron microscope analysis often have low dielectric constants, which reduces the overall capacitance of a transistor and, consequently, increases switching speed, improving the efficiency with which transistors including these materials may be manufactured may lead to faster, cheaper computers. As an additional example, the coating allows relatively small features of the structure to be observed, which assists in analyzing a semiconductor device.